1. The Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention is directed to improved fuse structure and methods for their manufacture.
2. The Relevant Technology
In order to improve yield in the manufacture of semiconductor devices, redundant circuit elements may be provided in a circuit layout. The redundant elements may be selectively connected to or disconnected from the circuit as needed to replace defective circuit elements by selectively blowing fuses in the circuit. In highly dense memory circuits, for example, spare rows and columns are formed during fabrication. If a defective bit is found during testing, a spare row or column is substituted for the defective bit by selectively blowing fuses included in the circuit for that purpose.
In state of the art memory circuit layouts, laser fuses take the form of sections of gate stacks including a polysilicon conductive layer. The stack is enclosed laterally by dielectric spacers and upwardly by a dielectric cap. A fuse is "blown" by irradiating the dielectric cap from above with laser radiation at a selected location along the gate stack. The polysilicon is heated by the laser radiation and expands, popping off the dielectric cap at the selected location, and the polysilicon is vaporized or burned off, creating a break in the conductive polysilicon layer.
Fabrication of reliable gate stack type fuses is complicated by the thickness of the overlying layers. As much as 30,000 to 40,000 Angstroms or more of overlying layers must be removed to expose the dielectric cap of the gate stack so that laser radiation may be used to blow a fuse. The overlying layers must be removed to within approximately 3000 Angstroms or less of the top of the cap in order for laser irradiation to reliably blow a selected fuse. But at etch depths as great as 30,000 or 40,000 Angstroms, variations in etch rate over the surface of a wafer, together with variations over the surface of the wafer in the layers to be etched resulting from previous process steps, can result in a difference as large as 6500 Angstroms or more between the deepest and shallowest effective depth of the etch. Etching too deep may destroy the gate stack or expose the substrate, allowing contamination and shorting. Etching not deep enough results in fuses that cannot be reliably blown.
Etching fuse openings thus typically requires painstaking control, such as a timed etch followed by an etch depth measurement for every wafer, followed by a second timed etch for a time calculated individually for each wafer. This type of control is cumbersome and time consuming. Even with control of this type, achieving an etch depth within process limits across the entire surface of a wafer is not always possible. Hence an improved method of etching fuse openings in a semiconductor device is needed.